Field
Embodiments of the present invention generally relate to methods and an apparatus of forming integrated circuits. More particularly, embodiments of the invention relate to methods and an apparatus for forming a gate electrode and associated layers.
Description of the Related Art
Integrated circuits may include more than one million micro-electronic devices such as transistors, capacitors, and resistors. One type of integrated circuit is field effect transistors (e.g., metal-oxide-semiconductor field effect transistors (MOSFET or MOS)) that are formed on a substrate (e.g., a semiconductor substrate) and cooperate to perform various functions within the circuit. A MOSFET transistor comprises a gate structure disposed between source and drain regions that are formed in the substrate. The gate structure generally comprises a gate electrode and a gate dielectric. The gate electrode is disposed over the gate dielectric to control a flow of charge carriers in a channel region formed between the drain and source regions beneath the gate dielectric. To increase the speed of the transistor, the gate may be formed from materials that lower the resistivity of the gate.
The gate dielectric layer may be formed of dielectric materials such as silicon dioxide (SiO2), or a high-k dielectric material having a dielectric constant greater than 4.0, such as SiON, SiN, hafnium oxide (HfO2), hafnium silicate (HfSiO2), hafnium silicon oxynitride (HfSiON), zirconium oxide (ZrO2), zirconium silicate (ZrSiO2), barium strontium titanate (BaSrTiO3, or BST), lead zirconate titanate (Pb(ZrTi)O3, or PZT), and the like. It should be noted, however, that the film stack may comprise layers formed of other materials.
Gate stacks may also incorporate metal layers formed on the high-k dielectric and on a polysilicon layer on the high-k dielectric. The metal layers may include Ti, TiN, W, WN, WSixNy or other metals.
Tungsten (W) may be particularly useful in gate electrodes and word and bit lines in DRAM types of integrated circuit devices because of its thermal stability during subsequent high temperature processes, where processing temperatures may reach 900° C. or more. Additionally, tungsten is a highly refractive material which offers good oxidation resistance and also lower resistivity. Melted, refined tungsten in bulk form typically has a resistivity of 5.5 μohms-cm. However, when tungsten is formed in thin films (e.g. less than 400 Å), the resistivity may be between 11-15 μohms-cm. For example, tungsten films formed using past PVD technology typically have a resistivity of 11-11.5 μohms-cm, whereas tungsten films formed using CVD technology typically have a resistivity of 13-15 μohms-cm.
Additionally, when thin film tungsten is combined with other materials such as WN or TiN, the resistivity of the tungsten film and the electrode stack may jump very high. For example, the resistivity of W on WN on polysilicon (poly) or tungsten on WSixNy on poly may be between 20-25 μohms-cm. In other examples, the resistivity of W on WN/Ti underlayer may be 15 μohms-cm or more and the resistivity of W on TiN may be as high as 30-40 μohms-cm. Lowering the resistivity of the tungsten film and as a result the gate electrode stack, may allow decreased dielectric thicknesses, reduced heights of the gate and distances between gate and bit lines, thereby improving overall switching speed of the gate electrode.
One solution for lowering the resistivity of tungsten on TiN is to insert tungsten silicide or silicon interlayers in between tungsten and TiN. Although this solution provides decreased resistivity, it requires the use of an additional chamber to deposit the silicon containing interlayer which increases processing time and correspondingly increases cost of ownership.
Further, in conventional MOS fabrication schemes, the substrate is required to pass between tools having the various reactors coupled thereto. The process of passing the substrate between tools necessitates the removal of the substrate from the vacuum environment of one tool for transfer at ambient pressures to the vacuum environment of a second tool. In the ambient environment, the substrates are exposed to mechanical and chemical contaminants, such as particles, moisture, and the like, that may damage the gate structures being fabricated and possibly form an undesired interfacial layer, e.g., native oxide, between each layer while transferring. As gate structures become smaller and/or thinner to increase the device speed, the detrimental effect of forming interfacial layers or contamination becomes an increased concern. Additionally, the time spent on transferring the substrate between the cluster tools decreases productivity in manufacture of the field effect transistors. Plus, advances in the reduction of critical dimension (CD) geometries of integrated circuits have also created a high demand for improved material properties.
Thus, although tungsten is a useful metal for gate electrodes, decreasing the resistivity of tungsten while reducing processing time may further help to improve gate electrode stack performance and modify the gate electrode materials to decrease the overall resistivity of the entire gate electrode stack. Therefore, there is a need in the art for methods and an apparatus for forming a gate stack that has improved properties.